The disclosure herein relates generally to semiconductor processing, and more particularly to fashioning a low noise junction field effect transistor (JFET). It can be appreciated that different electronic devices may have different requirements depending upon a particular device's application. For example, high performance precision analog applications may require very low noise, simple yet precise component matching, high speed and long term matching stability. In addition to demanding low component noise and precise component matching, precision analog products also require that operations of critical components be reliable and not modulated by other undesired sources such as overlying conducting metal buses. It would, therefore, be desirable to fashion transistors that operate with low noise, good matching and high disturbance immunity characteristics.
It can also be appreciated that transistors are basic building blocks of semiconductor circuitry and electronic devices. Accordingly, the type of transistor used depends upon the applications and the characteristics of the transistor. For example, junction field effect transistors (JFETs) generally exhibit very low 1/f noise and high input impedance. Complementary metal oxide semiconductor (CMOS) transistors, on the other hand, operate with a relatively higher level of noise and have a high impedance or low input current. Bipolar transistors, in contrast, accommodate good matching and, low noise, but exhibit a low impedance or a high input current. Given the desire for low noise in high performance precision analog applications and the propensity for JFET transistors to operate with low noise, it would thus be desirable to produce a JFET in a cost effective manner that allows the JFET to operate with even lower noise so that the JFET can be implemented in a high performance precision analog application.